Huawei’s Tau Scaling Law: A Chip-Design Workaround for the EUV Ban

At IEEE ISCAS 2026 in Shanghai, Huawei unveiled a chip-design principle that targets transistor density equivalent to 1.4-nanometre processes by 2031 by shortening signal paths instead of shrinking transistors, with the LogicFolding architecture already running in 381 mass-produced chips.
artificial-intelligence
Author

Kabui, Charles

Published

2026-06-01

Keywords

huawei-tau-scaling-law, logic-folding, semiconductor-design, euv-lithography, ascend-ai-chips